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Table operations have a similar problem with the two instructions addwf PCL, f and movwf PCL having a similar restriction to call and also can be located only in the rst 256 instructions of a page. This is due to the inability of accessing bit 8 of the address, and a zero is used in its place. PA0 in the STATUS register affects address bit 9, and PCL affects address bits 0 through 7. This restriction means that no tables can be longer than 256 instructions in low-end PIC microcontrollers. There are two other restrictions you also should be aware of for low-end devices. The rst is the availability of only two positions on the program counter stack. This means that there can only be one nesting level in low-end applications. Subroutines that have been called by other subroutines cannot call subroutines themselves. This is not a particularly onerous restriction because the number of nesting levels in all PIC microcontrollers is quite limited. When you are beginning to develop applications for the PIC microcontroller, I don t recommend using many nested subroutines because of the possibility of interrupts causing the program counter to over ow the stack and return addresses being lost in some cases. The second restriction is the availability of only a retlw (return from subroutine after loading the w register with a constant) instruction for returning from subroutines. There is no return statement in low-end PIC microcontrollers. In early versions of MPASM, when a return instruction was encountered in a lowend application, it would convert the instruction into

In an earlier version of MPLAB IDE, this message was not produced, and the assembler automatically inserted the retlw 0 instruction This caused me several hours of confusion one night trying to gure out why code that ran ne in a mid-range PIC microcontroller wouldn t work in a low-end device To avoid this problem, you may wish to always return values in a subroutine in a common variable rather than in the w register or use the STATUS ags to return pass/fail or other binary information No interrupts in low-end PIC microcontrollers changes the way inputs and hardware events are monitored Instead of waiting for an event, your code will have to poll for the event If a signal waited for is very short, you may miss it.

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In Appendix G, I have a small snippet of code that will set up TMR0 of PIC microcontrollers to over ow when a signal is received This will allow you to use the TMR0 hardware in the PIC microcontroller to indicate if a pulse has been received or a line has changed state without having to continually poll it The last difference, the lack of bank select bits, will be the biggest issue you have in porting mid-range applications to low-end devices The most obvious problem will be the need to convert all the bank switch writes to the OPTION_REG and the TRIS registers to the single-instruction equivalents, but there is a larger problem you should be aware of In low-end devices, a register bank uses only 5 bits for addressing (in high-end devices, 7 address bits for each address are used).

This only gives a maximum of 32 registers per bank There can be up to four banks, each with shared INDF, TMR0, PCL, STATUS, FSR, PORTA, PORTB, PORTC, and le registers The top 16 registers are usually left as being unique to each bank This layout leaves a maximum of 25 bytes for an array, with 16 being the maximum in any bank other than bank 0 The low-end register organization looks like Fig 85, and in low-end PIC microcontroller devices, even though a total of 7 address bits are used when all four banks are taken into account, only a maximum of 73 unique addresses are implemented, with 48 of them accessible only by the FSR In most mid-range devices, the registers in each bank are unique to that bank, although there are shadowed registers to allow data movement between banks.

In low-end devices, the rst 16 registers of each bank are shared (or shadowed ) between the maximum four banks Another issue to be aware of with low-end devices and their restricted register banking operation is that the FSR index register can never be equal to 0 Because of this, make sure that you never write any application code such as.

Bank 0 Addr - Reg 00 - INDF 01 - TMR0 02 - PCL 03 - STATUS 04 - FSR 05 - PORTA* 06 - PORTB 07 - PORTC 08-0F Shared File Regs 10-1F Bank 0 File Regs

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Bank 1 Addr - Reg 20 - INDF 21 - TMR0 22 - PCL 23 - STATUS 24 - FSR 25 - PORTA* 26 - PORTB 27 - PORTC 28-2F Shared File Regs 30-3F Bank 1 File Regs

1.1 The belt speed of the process described in Fig. 1.2 is 12 ft/min, and the weigh cell is located 4 ft from the valve. Estimate the natural period under integral control and the reset, time required for +p-amplitude damping. Is this setting likely to be conservative W h y 1 .P The same process is to be controlled with a proportional-plus-reset controller, adjusted for a reset phase lag of 60 : Calculate the settings required for %-amplitude damping, and check your answer against Table 1.1.

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